Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. In this regard, PLDs typically include logic blocks that are used to perform various logic operations. These logic blocks may be interconnected through signal paths provided by various wires and switches of the PLD. Interconnections between programmable logic blocks, wires, and switches may be specified by a routing graph of the PLD prepared, for example, by appropriate software running on a computing system.
However, software representations of routing graphs often consume substantial amounts of computing system memory due to the potentially large numbers of programmable logic blocks, wires, switches, and related interconnections identified by the routing graphs. In some cases, such memory sizes may exceed the memory available of a given computing system.
As a result, techniques have been developed to reduce the size of memory used to represent routing graphs. In one such approach, a routing graph may be divided into a small number of sub-graphs which may share similar layout patterns. In this approach, however, boundaries between the sub-graphs may be treated as special conditions which nevertheless require large amounts of memory to represent wires spanning more than one sub-graph.
As a result, there is a need for an improved way of representing interconnections between PLD components. In particular, there is a need for an approach to identifying routing graph interconnections between PLD components that facilitates efficient storage of such information.